`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn
// 
// Create Date: 2021/11/20 17:02:22
// Design Name: HW1
// Module Name: tb_BCD_prior_encoder
// Project Name: hw1
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: testbench for Homework 1 for Fudan PLD & HDL courses
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_BCD_prior_encoder;
    reg [9:0] swchin;
    wire [3:0] codeout;
    wire E;
    integer i;
    initial begin
        swchin <= 10'b1111111111;
    end

    initial begin
        for(i=0;i<1024;i=i+1)
            #5 swchin = swchin - 1;
        #5 $finish;
    end 

BCD_prior_encoder inst_BCD_prior_encoder(swchin,E,codeout);
endmodule
